(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a complimentary metal oxide semiconductor (CMOS), device, using a process featuring super-steep retrograde (SSR), twin wells, and double selective epitaxial growth.
(2) Description of Prior Art
Micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features have allowed device performance to be increased, while the processing cost for a specific semiconductor chip comprised with devices formed with sub-micron features has been reduced. The reduced dimensions have resulted in decreases in performance degrading parasitic capacitances, while smaller semiconductor chips, still providing device densities equal to, or greater than counterpart larger chips, allow a greater number of semiconductor chips to be obtained from a specific size semiconductor wafer thus reducing the processing cost for a specific semiconductor chip. However performance increases experienced with devices formed with sub-micron features, can present reliability as well as yield concerns not present for devices formed using larger features. Channel lengths, the region under the gate structure located between source/drain regions, have now been reduced to levels less than 0.15 um. These sub-micron channel lengths although providing performance enhancements, can also result in unwanted short channel effects as well as reduced carrier mobility. Formation of well regions, offering increased doping at the top portion of the channel region can reduce short channel effects as well as increasing carrier mobility, however at the expense of increasing the threshold voltage of the device. Since power consumption is an important characteristic parameter for devices used for cellular telephones and notebook computers, the higher threshold voltage resulting from the use of conventional well regions, is not an acceptable solution.
The use of super-steep retrograde (SSR), well regions, featuring a peak dopant concentration needed to reduce short channel effects, located in the center of the SSR well region, and a lower dopant concentration located at the top surface of the SSR well region, needed to allow the use of a lower threshold voltage, can be used to optimize these device characteristics. The present invention will provide a method of fabricating a CMOS device featuring integration of an SSR twin-well region with an isolation structure, using two selective epitaxial growth (SEG) procedures. The simplified process of integrating SSR twin-well regions and isolation structures, described in this present invention, will feature reduced implantation energies for formation of the well regions, however still providing the needed dopant concentrations for minimizing short channel effects. Prior art such as: Augusto, in U.S. Pat. No. 6,143,593; Nandakumar et al, in U.S. Pat. No. 6,228,725 B1; Borland, in U.S. Pat. No. 6,187,643 B1; and Son et al, in U.S. Pat. No. 6,137,141, have described processes for forming semiconductor devices, some comprised with SSR wells, and some formed using selective epitaxial growth procedures. These prior arts however do not describe the novel procedure now described in the present invention in which a combination of process steps, such as double SEG, as well as integration of SSR well regions and isolation structures, are used to fabricate a CMOS device with reduced risk of short channel effects, while still providing a channel region which allows a low threshold voltage to be realized.
It is an object of this invention to fabricate a CMOS device featuring the integration of SSR twin-well regions and isolation structures.
It is another object of this invention to use two selective epitaxial growth procedures to provide the silicon shapes for the twin well regions.
It is still another object of this invention to provide an initial silicon shape, formed via a first SEG procedure, to accept the implanted ions for the SSR twin well regions, followed by a second SEG and anneal procedure, allowing the final profile for the SSR twin well regions, to be defined in a final, or in a composite silicon shape.
In accordance with the present invention a process for fabricating a CMOS device, featuring the integration of SSR twin well regions and isolation features, achieved via implementation of two SEG procedures, is described. After formation of insulator shapes on a semiconductor substrate, a first selective epitaxial growth (SEG), procedure is used to place bottom silicon shapes on portions of the semiconductor substrate not occupied by the insulator shapes. A first bottom silicon shape, located in a region of the semiconductor substrate to be used for a P channel metal oxide semiconductor (PMOS) device, is subjected to an N type ion implantation procedure placing N type ions in a specific portion of the first bottom silicon shape needed for an SSR N well region, while a second bottom silicon shape, located in a region of the semiconductor substrate to be used for an N channel metal oxide semiconductor (NMOS), device, is subjected to a P type ion implantation procedure placing P type ions in a specific portion of the second bottom silicon shape, needed for an SSR P well region. A second SEG procedure is next employed resulting in final silicon shapes, each comprised of an overlying top silicon shape and underlying bottom silicon shape. An anneal procedure is next performed resulting in the formation of a SSR N well region in the final, or composite silicon shape of the PMOS region, and resulting in the formation of a SSR P well region in the final silicon shape located in the NMOS region, with the highest concentration of dopants located in the underlying bottom silicon shapes, while a lower dopant region is located in the top portion of the overlying, top silicon shapes. After growth of a gate insulator layer, and definition of gate structures, implanted pocket or halo regions and lightly doped source/drain regions are formed in the final silicon shapes of both PMOS and NMOS regions, not covered by gate structures. After formation of insulator spacers on the sides of the gate structures, heavily doped source/drain regions are formed in portions of the final silicon shapes not covered by gate structures or by insulator spacers.